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twindie ? ddr2 sdram mt47h1g4 C 64 meg x 4 x 8 banks x 2 ranks MT47H512M8 C 32 meg x 8 x 8 banks x 2 ranks features ? uses 2gb micron die ? two ranks (includes dual cs#, odt, and cke balls) ? each rank has 8 internal banks for concurrent oper- ation ? v dd = v ddq = +1.8v 0.1v ? jedec-standard 63-ball fbga ? low-profile package C 1.35mm max thickness functionality the 4gb (twindie ? ) ddr2 sdram uses microns 2gb ddr2 monolithic die and has similar functionali- ty. this twindie data sheet is intended to provide a general description, package dimensions, and the ballout only. refer to micron's 2gb ddr2 data sheet for complete information or for specifications not in- cluded in this document. options marking ? configuration C 64 meg x 4 x 8 banks x 2 ranks 1g4 C 32 meg x 8 x 8 banks x 2 ranks 512m8 ? fbga package (pb-free) C 63-ball fbga (9mm x 11.5mm) rev. c wtr ? timing C cycle time 1 C 2.5ns @ cl = 5 (ddr2-800) -25e C 2.5ns @ cl = 6 (ddr2-800) -25 C 3.0ns @ cl = 5 (ddr2-667) -3 C 3.75ns @ cl = 4 (ddr2-533) -37e ? self refresh C standard none ? operating temperature C commercial (0c t c 85c) none ? revision :c note: 1. cl = cas (read) latency. table 1: key timing parameters speed grade data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) t rfc (ns) cl = 3 cl = 4 cl = 5 cl = 6 -25e 400 533 800 800 12.5 12.5 55 197.5 -25 400 533 667 800 15 15 55 197.5 -3 400 533 667 n/a 15 15 55 197.5 -37e 400 533 n/a n/a 15 15 55 197.5 table 2: addressing parameter 1 gig x 4 512 meg x 8 configuration 64 meg x 4 x 8 banks x 2 ranks 32 meg x 8 x 8 banks x 2 ranks refresh count 8k 8k row address a[14:0] (32k) a[14:0] (32k) bank address ba[2:0] (8) ba[2:0] (8) column address a[11, 9:0] (2k) a[9:0] (1k) 4gb: x4, x8 twindie ddr2 sdram features pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
ball assignments and descriptions figure 1: 63-ball fbga C x4, x8 ball assignments (top view) 1 2 3 4 6 7 8 9 5 v dd nf, dq6 v ddq nf, dq4 v ddl ba2 cke1 v ss v dd nf, nu/rdqs# v ssq dq1 v ssq v ref cke0 ba0 a10 a3 a7 a12 v ss dm, rdqs v ddq dq3 v ss we# ba1 a1 a5 a9 a14 v ssq dqs v ddq dq2 v ssdl ras# cas# a2 a6 a11 rfu v ddq nf, dq7 v ddq nf, dq5 v dd odt0 cs1# v dd odt1 v ss dqs#/nu v ssq dq0 v ssq ck ck# cs0# a0 a4 a8 a13 a b c d e f g h j k l note: 1. dark balls (with ring) designate balls that differ from the monolithic versions. 4gb: x4, x8 twindie ddr2 sdram ball assignments and descriptions pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 3: fbga 63-ball descriptions symbol type description a[14:0] input address inputs: provide the row address for activate commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge com- mand determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. ba[2:0] input bank address inputs: ba[2:0] define to which bank an activate, read, write, or pre- charge command is being applied. ba[2:0] define which mode register including mr, emr, emr(2), and emr(3) is loaded during the load mode command. ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dq and dqs/dqs#) is referenced to the crossings of ck and ck#. cke[1:0] input clock enable: cke (registered high) activates and cke (registered low) deactivates clocking circuitry on the ddr2 sdram. the specific circuitry that is enabled/disabled is dependent on the ddr2 sdram configuration and operating mode. cke low provides precharge power-down and self refresh operations (all banks idle), or activate pow- er-down (row active in any bank). cke is synchronous for power-down entry, power- down exit, output disable, and for self refresh entry. cke is asynchronous for self re- fresh exit. input buffers (excluding ck, ck#, cke, and odt) are disabled during power- down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_18 input but will detect a lvcmos low level once v dd is applied during first pow- er-up. after v ref has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self-refresh operation, v ref must be maintained. cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for exter- nal bank selection on systems with multiple ranks. cs# is considered part of the com- mand code. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm balls are input-only, the dm loading is designed to match that of dq and dqs balls. odt[1:0] input on-die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is only applied to each of the following balls: dq[7:0], dqs, dqs#, and dm. the odt input will be ignored if disabled via the load mode command. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. dq[3:0] i/o data input/output: bidirectional data bus for x4 configuration. dq[7:0] i/o data input/output: bidirectional data bus for x8 configuration. dqs, dqs# i/o data strobe: output with read data, input with write data for source synchronous oper- ation. edge-aligned with read data, center-aligned with write data. dqs# is only used when differential data strobe mode is enabled via the load mode command. 4gb: x4, x8 twindie ddr2 sdram ball assignments and descriptions pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 3: fbga 63-ball descriptions (continued) symbol type description rdqs, rdqs# i/o redundant data strobe: for the x8 configuration only. rdqs is enabled/disabled via the load mode command to the extended mode register (emr). when rdqs is enabled, rdqs is output with read data only and is ignored during write data. when rdqs is disa- bled, ball b3 becomes data mask (see dm ball). rdqs# is only used when rdqs is enabled and differential data strobe mode is enabled. v dd supply power supply: 1.8v 0.1v. v ddq supply dq power supply: 1.8v 0.1v. isolated on the device for improved noise immunity. v ddl supply dll power supply: 1.8v 0.1v. v ref supply sstl_18 reference voltage (v ddq /2). v ss supply ground. v ssdl supply dll ground: isolated on the device from v ss and v ssq . v ssq supply dq ground: isolated on the device for improved noise immunity. nf C no function: these balls are no function on the x4 configuration. nu C not used: for the x8 configuration only. if emr(e10) = 0, a2 = rdqs# and a8 = dqs#. if emr(e10) = 1, a2 and a8 are not used. rfu C reserved for future use. 4gb: x4, x8 twindie ddr2 sdram ball assignments and descriptions pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
functional description the 4gb (twindie) ddr2 sdram is a high-speed, cmos dynamic random access memory device containing 4,294,967,296 bits and internally configured as two 8-bank 2gb ddr2 sdram devices. although each die is tested individually within the dual-die package, some twindie test results may vary from a like-die tested within a monolithic die package. each ddr2 sdram die uses a double data rate architecture to achieve high-speed op- eration. the ddr2 architecture is essentially a 4 n -prefetch architecture, with an inter- face designed to transfer two data words per clock cycle at the i/o balls. a single read or write access consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the inter- nal dram core and four corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o balls. addressing of the twindie is identical to the monolithic device. additionally, multiple chip selects select the desired rank. this twindie data sheet is intended to provide a general description, package dimen- sions, and the ballout only. refer to the micron 2gb ddr2 data sheet for complete in- formation regarding individual die initialization, register definition, command descrip- tions, and die operation. 4gb: x4, x8 twindie ddr2 sdram functional description pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
functional block diagrams figure 2: 64 meg x 4 x 8 banks x 2 ranks cs0# cke0 odt0 cs1# cke1 odt1 cas# ras# we# ck ck# dq[3:0] dqs, dqs# dm a[14:0] ba[2:0] rank 0 (64 meg x 4 x 8 banks) rank 1 (64 meg x 4 x 8 banks) 4gb: x4, x8 twindie ddr2 sdram functional block diagrams pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
figure 3: 32 meg x 8 x 8 banks x 2 ranks cs0# cke0 odt0 cs1# cke1 odt1 cas# ras# we# ck ck# dq[7:0] dqs, dqs#, rdqs, rdqs# dm a[14:0] ba[2:0] rank 0 (32 meg x 8 x 8 banks) rank 1 (32 meg x 8 x 8 banks) 4gb: x4, x8 twindie ddr2 sdram functional block diagrams pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
electrical specifications C absolute ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions oustide those indicated in the operational sections of this specification is not im- plied. exposure to absolute maximum rating conditions for extended periods may ad- versely affect reliability. table 4: absolute maximum dc ratings parameter symbol min max units notes v dd supply voltage relative to v ss v dd 1.0 2.3 v 1 v ddq supply voltage relative to v ssq v ddq 0.5 2.3 v 1, 2 v ddl supply voltage relative to v ssl v ddl 0.5 2.3 v 1 voltage on any ball relative to v ss v in , v out 0.5 2.3 v 3 input leakage current; any input 0v v in v dd ; all other balls not under test = 0v i i 10 10 a output leakage current; 0v v out v ddq ; dq and odt disabled i oz 10 10 a v ref leakage current; v ref = valid v ref level i vref 4 4 a notes: 1. v dd , v ddq , and v ddl must be within 300mv of each other at all times; this is not re- quired when power is ramping down. 2. v ref 0.6 x v ddq ; however, v ref may be v ddq provided that v ref 300mv. 3. voltage on any i/o may not exceed voltage on v ddq . temperature and thermal impedance it is imperative that the ddr2 sdram devices temperature specifications, shown in the following table, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. an important step in main- taining the proper junction temperature is using the devices thermal impedances cor- rectly. the thermal impedances are listed in table 6 (page 9)for the applicable and available die revision and packages. incorrectly using thermal impedances can produce significant errors. read micron technical note tn-00-08, thermal applications, prior to using the thermal impedan- ces listed below. for designs that are expected to last several years and require the flexi- bility to use several dram die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size re- duction. the ddr2 sdram devices safe junction temperature range can be maintained when the t c specification is not exceeded. in applications where the devices ambient tem- perature is too high, use of forced air and/or heat sinks may be required in order to sat- isfy the case temperature specifications. 4gb: x4, x8 twindie ddr2 sdram electrical specifications C absolute ratings pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 5: temperature limits parameter symbol min max units notes storage temperature t stg C55 150 c 1 operating temperature: commercial t c 0 85 c 2, 3 notes: 1. max storage case temperature t stg is measured in the center of the package, as shown in the figure below. this case temperature limit is allowed to be exceeded briefly during package reflow, as noted in micron technical note tn-00-15, recommended soldering parameters. 2. max operating case temperature t c is measured in the center of the package, as shown below. 3. device functionality is not guaranteed if the device exceeds maximum t c during operation. figure 4: example temperature test point location test point lmm x wmm fgba 0.5 (w) 0.5 (l) length (l) width (w) table 6: thermal impedance die revision package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) notes c 63-ball 2-layer 62.6 45.3 39.2 28.5 3.5 1 4-layer 45.8 36.5 32.9 28.1 note: 1. thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. 4gb: x4, x8 twindie ddr2 sdram electrical specifications C absolute ratings pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
electrical specifications C i cdd parameters table 7: ddr2 i dd specifications and conditions (die revision c) notes: 1C8 apply to the entire table parameter/condition com- bined symbol individual die status bus width -25e/ -25 -3e/-3 units operating one bank active-precharge current : t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching (inactive die is in i dd2p condition, but with inputs switching) i cdd0 i cdd0 = i dd0 + i cdd2p x4, x8 92 87 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w (inactive die is in i dd2p condition, but with inputs switching) i cdd1 i cdd1 = i dd1 + i cdd2p x4, x8 107 102 ma precharge power-down current: all banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i cdd2p i cdd2p = i dd2p + i dd2p x4, x8 24 24 ma precharge quiet standby current: all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating i cdd2q i cdd2q = i dd2q + i dd2p x4, x8 47 42 ma precharge standby current: all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus in- puts are switching; data bus inputs are switching (inactive die is in i dd2p condition, but with inputs switching) i cdd2n i cdd2n = i dd2n + i cdd2p x4, x8 52 47 ma active power-down current: all banks open; t ck = t ck (i dd ); cke is low; other control and address bus in- puts are stable; data bus inputs are floating (individual die status: i cdd3p = i dd3p + i dd2p ) i cdd3p fast pdn exit mr[12] = 0 x4, x8 42 37 ma slow pdn exit mr[12] = 1 x4, x8 26 26 active power-down current: all banks open; t ck = t ck (i dd ); cke is low; other control and address bus in- puts are stable; data bus inputs are floating (individual die status: i cdd3p = i dd3p + i dd2p ) i cdd3n i cdd3n = i dd3n + i cdd2p x4, x8 62 57 ma active standby current: all banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching (inac- tive die is in i dd2p condition, but with inputs switching) i cdd4w i cdd4w = i dd4w + i cdd2p x4, x8 162 142 ma operating burst read current: all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching (inactive die is in i dd2p condition, but with inputs switching) i cdd4r i cdd4r = i dd4r + i cdd2p x4, x8 162 142 ma 4gb: x4, x8 twindie ddr2 sdram electrical specifications C i cdd parameters pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 7: ddr2 i dd specifications and conditions (die revision c) (continued) notes: 1C8 apply to the entire table parameter/condition com- bined symbol individual die status bus width -25e/ -25 -3e/-3 units burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc(i dd ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching (inactive die is in i dd2p condition, but with inputs switching) i cdd5 i cdd5 = i dd5 + i cdd2p x4, x8 197 177 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i cdd6 i cdd6 = i dd6 + i dd6 x4, x8 24 24 ma operating bank interleave read current: all bank inter- leaving reads, iout = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (idd); cke is high, cs# is high be- tween valid commands; address bus inputs are stable during deselects; data bus inputs are switching (inactive die is in i dd2p condition, but with inputs switching) i cdd7 i cdd7 = i dd7 + i cdd2p x4, x8 262 237 ma notes: 1. i cdd /i dd specifications are tested after the device is properly initialized. 0c t c +85c. v dd = v ddq = +1.8v 0.1v; v ddl = +1.8v 0.1v; v ref = v ddq /2. 2. i cdd /i dd parameters are specified with odt disabled. 3. data bus consists of dq, dm, dqs, dqs#, rdqs, and rdqs#. idd values must be met with all combinations of emr bits 10 and 11. 4. i cdd /i dd values must be met with all combinations of emr bits 10 and 11. 5. definitions for i cdd /i dd conditions: low v in(ac) v il(ac)max high v in v ih(ac)min stable inputs stable at a high or low level floating inputs at v ref = v ddq /2 switching inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals switching inputs changing between high and low every other data transfer (once per clock) for dq signals, not including masks or strobes 6. i dd1 , i dd4r , and i dd7 require a12 in emr1 to be enabled during testing. 7. i cdd values reflect the combined current of both individual die. i ddx represents individual die values. 8. the following i dd values must be derated (i dd limits increase) on it-option or on at-op- tion devices when operated outside of the range 0c t c 85c: when t c 0c i dd2p and i dd3p(slow) must be derated by 4%; i dd4r and i dd5w must be derat- ed by 2%; and i dd6 and i dd7 must be derated by 7% when t c 85c i dd0 , i dd1 , i dd2n , i dd2q , i dd3n , i dd3p(fast) , i dd4r , i dd4w , and i dd5w must be de- rated by 2%; i dd2p must be derated by 20%; i dd3p slow must be derated by 30%; and i dd6 must be derated by 80% (i dd6 will increase by this amount if t c < 85c and the 2x refresh option is still enabled) 4gb: x4, x8 twindie ddr2 sdram electrical specifications C i cdd parameters pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
package dimensions figure 5: 63-ball fbga (9mm x 11.5mm) (wtr) ball a1 id seating plane 0.12 a a 0.8 0.1 1.2 max 0.25 min 9 0.15 ball a1 id 8 ctr solder ball material: sac305. dimensions apply to solder balls post-reflow on ?0.33 nsmd ball pads. 63x ?0.45 11.5 0.15 0.8 typ 0.8 typ 6.4 ctr 9 8 7 3 2 1 a b c d e f g h j k l note: 1. all dimensions are in millimeters. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. twindie is a trademark of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 4gb: x4, x8 twindie ddr2 sdram package dimensions pdf: 09005aef8227ee4d mt47h1g_64m_32m_twindie.pdf - rev. i 01/14 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.

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